1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular to an IC tester having a multiple period generators.
2. Description of Related Art
A typical per-pin integrated circuit tester includes a pattern generator and a set of tester channels, one for each pin of an integrated circuit device under test (DUT). The tester organizes a test into a set of successive test cycles, and during each test cycle each channel carries out a test activity at a corresponding DUT pin. Test activities may include supplying a test signal to the DUT pin or monitoring a DUT output signal produced at the pin. Before the start of each test cycle the pattern generator supplied data to each channel indicating the test activity to be carried out during the test cycle. In prior art test systems, the length of a test cycle is the same for all channels. However in some tests, test activities may occur at some pins at a higher frequency than others. For example a given DUT may have several pins which could be tested at one frequency but may require an input clock signal having twice that frequency. Since the test cycle must be the same for all channels, the test must be carried out at the higher frequency. Thus the pattern generator must produce channel input data at twice the frequency needed for all the lower frequency channels. This increases the amount of data that the pattern generator must store and thus increases tester programming time and limits maximum test length.
What is needed is an integrated circuit tester which allows test to be carried out with tester periods that may vary from channel-to-channel and from time-to-time during a test.